ECL to CMOS translator

ABSTRACT

In integrated circuits which include both ECL and CMOS circuits, there is an ECL to CMOS translator which converts ECL logic levels to CMOS logic levels. To convert from ECL to CMOS levels, the ECL logic high is coupled to the base of an NPN transistor which provides a CMOS logic low. The ECL logic low is prevented from being coupled to the base of the NPN transistor. The CMOS logic high is obtained by an analogous second circuit which is responsive to a complementary ECL signal the output of which is coupled to a P channel transistor. The P channel transistor either provides the CMOS logic high output or is non-conductive.

FIELD OF THE INVENTION

The present invention relates to BiMOS integrated circuits, and moreparticularly, to BiMOS integrated circuits which have an ECL circuitwhich outputs a signal to a CMOS circuit.

BACKGROUND OF THE INVENTION

Integrated circuit processing technology has been developed which allowsfor the formation of bipolar and MOS circuits on the same die (orchips). Bipolar and MOS circuits have different characteristics whichcan be used to complement each other. Bipolar circuits tend to be fasterthan MOS circuits whereas MOS circuits tend to consume less power thanbipolar circuits. The low power of MOS allows for, among other things,more transistors on a chip. This is particularly advantageous inmemories. Bipolar and MOS circuits have been combined on the same chipin static random access memories (SRAMs) for example.

In such a memory the bipolar circuits are used primarily in theperipheral circuitry for speed. Some of the peripheral circuits areCMOS. The memory array itself is MOS circuitry for density. The signalsgenerated externally are received by bipolar circuitry and theninternally provided to CMOS circuits. There must then be providedinternally a circuit for making the transition from bipolar levelsignals to CMOS level signals.

In the case where emitter coupled logic (ECL) circuits are used as thebipolar circuits, there is a particular problem with level translationbecause ECL logic states vary only about one volt whereas CMOS logicstates swing the full rail of the power supply voltage. The typicalpower supply voltage is about 5 volts. That the difference between alogic high and a logic low is only one volt in ECL is part of the reasonthat ECL circuits are so fast. On the other hand a part of the reasonthat CMOS is low power is because the logic levels swing the entirepower supply voltage. One of the requirements then of an integratedcircuit which combines the advantages of CMOS and ECL is that there bean ECL to CMOS translator which does not cause excessive delay. In thepast this translation has been accomplished by having a P channel devicereceive the ECL signal. This has created problems because the P channeldevice must be made very large because the one volt logic statedifferential of ECL does not cause a very large gate to source voltagedifferential on the P channel transistor. The ECL transistors do nottrack the P channel transistors over process variations so there is alsoa problem in guaranteeing that the P channel transistor isnon-conductive for the logic high output of the ECL circuit.

SUMMARY OF THE INVENTION

An object of the invention is to provide an improved ECL to CMOStranslator.

This and other objects are provided in an integrated circuit having anECL circuit for providing a first ECL output signal at a logic low at avoltage at least 2 volts above a voltage at a first power supplyterminal and a logic high at a voltage greater than the voltage of thelogic low and further having a translator circuit for providing avoltage at or near the potential at the first power supply terminal onan output node in response to the ECL output signal switching to thelogic high. The translator circuit comprises a first NPN transistor, acontrol circuit, and a second transistor. The first NPN transistor has abase for receiving the first ECL output signal, a collector coupled to asecond power supply terminal for receiving a voltage greater than thevoltage present at the second power supply terminal, and an emitter. Thecontrol circuit couples the emitter of the first NPN transistor to anintermediate node in response to said ECL output signal switching to thelogic high and prevents the emitter of the first NPN transistor frombeing coupled to the intermediate node when said ECL output signal is atthe logic low. The second transistor has a control electrode coupled tothe intermediate node, a first current electrode coupled to the firstpower supply terminal, and a second current electrode coupled to theoutput node. The output node is thus coupled to the first power supplyterminal in response to the first ECL output signal switching to thelogic high.

BRIEF DESCRIPTION OF THE DRAWINGS

The FIGURE is a combination circuit and block diagram of an ECL to CMOStranslator according to a preferred embodiment of the invention.

DESCRIPTION OF THE INVENTION

Shown in the sole FIGURE is an ECL to CMOS translator 10 comprising anNPN transistor 11, a P channel transistor 12, a P channel transistor 13,a resistor 14, a reference generator 15 for generating a referencevoltage VR, a resistor 16, an NPN transistor 17, an inverter 18, an Nchannel transistor 19, a diode 20, a P channel transistor 21, an NPNtransistor 22, an NPN transistor 23, a P channel transistor 24, a Pchannel transistor 26, a resistor 27, a resistor 28, an NPN transistor29, an inverter 31, an N channel transistor 32, a diode 33, a P channeltransistor 34, and an NPN transistor 36.

Transistor 11 has a collector coupled to a positive power supplyterminal VCC for receiving a positive power supply voltage of, forexample, 5 volts, a base for receiving a true ECL input signal IN, andan emitter. Transistor 12 has a source connected to the emitter oftransistor 11, a gate for receiving reference voltage VR from referencevoltage generator 15, and a drain. Transistor 13 has a source connectedto the drain of transistor 12, a gate, and a drain. Resistor 14 has afirst terminal connected to the drain of transistor 13, and a secondterminal. Resistor 16 has a first terminal connected to the secondterminal of resistor 16, and a second terminal connected to ground.Transistor 17 has a base connected to the first terminal of resistor 14,a collector connected to the emitter of transistor 11, and an emitterconnected to the second terminal of resistor 14. Inverter 18 has aninput connected to an output node 41, and an output connected to thegate of transistor 13. Transistor 19 has a gate connected to the outputof inverter 18, a drain connected to the input of inverter 18, and asource connected to ground. Diode 20 has an anode connected to the firstterminal of resistor 14, and a cathode connected to node 41. Transistor21 has source connected to VCC, a drain connected to node 41, and a gateconnected to an output node 42. Transistor 22 has a collector connectedto node 41, a base connected to the second terminal of resistor 14, andan emitter connected to ground.

Transistor 23 has a collector connected to VCC, a base for receiving acomplementary ECL input signal *IN, and an emitter. Transistor 24 has asource connected to the emitter of transistor 23, a gate for receivingreference voltage VR, and a drain. Transistor 26 has a source connectedto the drain of transistor 24, a gate, and a drain. Resistor 27 has afirst terminal connected to the drain of transistor 26, and a secondterminal. Resistor 28 has a first terminal connected to the secondterminal of resistor 27, and a second terminal connected to ground.Transistor 29 has a base connected to the first terminal of resistor 27,a collector connected to the emitter of transistor 23, and an emitterconnected to the second terminal of resistor 27. Inverter 31 has aninput connected to the output node 42, and an output connected to thegate of transistor 26. Transistor 32 has a gate connected to the outputof inverter 31, a drain connected to the input of inverter 31, and asource connected to ground. Diode 33 has an anode connected to the firstterminal of resistor 27, and a cathode connected to node 42. Transistor34 has source connected to VCC, a drain connected to node 42, and a gateconnected to an output node 41. Transistor 36 has a collector connectedto node 42, a base connected to the second terminal of resistor 27, andan emitter connected to ground.

Translator 10 can be viewed as having a true responsive circuit 51 and acomplementary responsive circuit 52. Circuit 51 receives true signal INas an input, whereas circuit 52 receives complementary signal *IN as aninput. Circuit 51 comprises transistors 11, 12, 13, 17, 19, 21, and 22;resistors 14 and 16; inverter 18; and diode 20. Circuit 52 comprisestransistors 23, 24, 26, 29, 32, 34, and 36; resistors 27 and 28;inverter 31; and diode 33.

In operation signals IN and *IN are complementary signals generated byan ECL circuit. Nodes 41 and 42 are the nodes at which complementarysignals *F and F, respectively, are generated as full rail signals andthus suitable for use by a CMOS circuit. The control of the voltage onthe emitters of transistors 11 and 23, labelled nodes 43 and 44,respectively, is highly relevant to the operation of translator 10.

When signal IN is a logic high, transistor 11 drives node 43 to onebase-emitter drop (Vbe) below the voltage of signal IN. Referencevoltage VR is chosen so that transistor 12 is conductive when node 43 isone Vbe below the ECL logic high voltage. Assuming that output signal *Fis going to have to change state in response to signal IN switching to alogic high, signal *F will then be assumed to be a logic high. Withsignal *F at a logic high, inverter 18 outputs a logic low to transistor13 which causes transistors 13 to be conductive. With transistors 12 and13 conductive, current flows through transistors 12 and 13 and resistors14 and 16 which causes a voltage drop across resistors 14 and 16 and arise in voltage on the base of transistor 22 until transistor 22 becomesconductive. Transistor 22 becoming conductive causes node 41 to bereduced in voltage. The rise in voltage on resistors 14 and 16 alsocauses transistor 17 to conduct passing even more current to the base ontransistor 22 which causes transistor 22 to even more rapidly reduce thevoltage at node 41. As node 41 reduces in voltage, inverter 18 respondsby outputting a logic high which causes transistor 13 to becomenon-conductive. As transistor 13 becomes non-conductive, current stopsflowing through resistors 14 and 16 to reduce the voltage on the basesof transistors 17 and 22 until transistors 17 and 22 becomenon-conductive. Diode 20 also prevents transistor 22 from becomingsaturated when transistor 22 is conductive and speeds up how fasttransistors 17 and 22 become completely non-conductive. Transistor 19pulls node 41 to ground and ensures that node 41 is held at a logic lowafter transistor 22 has become non-conductive. The logic low on node 41causes transistor 34 to become conductive and drive node 42 to a logichigh. Thus circuit 51 responds to signal IN switching to a logic high byswitching signal *F to a logic low which causes signal F to switch to alogic high.

For the case in which signal IN switches to a logic low from a logichigh, the initial condition of node 43 is one Vbe below the logic highstate of signal IN so that transistor 12 is conductive. Transistor 13 isnon-conductive because inverter 18 outputs a logic high in response tothe logic low of signal *F. When signal IN does switch to a logic low,node 43 will initially drop slightly in voltage due to base-emittercapacitance of transistor 11 but there is otherwise initially noresponse to signal IN switching to a logic low. Signal *F is switched toa logic high in response to circuit 52 switching signal F to a logic lowin response to signal *IN switching to a logic high. As complementarysignals, if signal IN switches to a logic low, then it is known thatsignal *IN will switch to a logic high. Circuit 52 operates to providesignal F at a logic low in response to signal *IN switching to a logichigh in the same manner as described for circuit 51 providing signal *Fat a logic low in response to signal IN switching to a logic high.Signal F switching to a logic low causes transistor 21 to becomeconductive which causes node 41 to rise in voltage. Transistor 21 isquite large in gain compared to that of transistor 19, which is merely akeeper device, so that transistor 21 easily overdrives transistor 19 todrive node 41 higher in voltage so that signal *F becomes a logic high.As node 41 rises in voltage, inverter 18 responds by outputting a logiclow which causes transistor 13 to become conductive. With transistors 12and 13 conductive, node 43 is reduced in voltage until transistor 12becomes non-conductive. Transistor 12 will become non-conductive whennode 43 is reduced to one P channel threshold voltage above referencevoltage VR. Transistor 11 is non-conductive so that the voltage at node43 is maintained because of capacitance of the source of transistor 12,the emitter of transistor 11, and the collector of transistor 17. Thusthe amount of charge drawn from node 43 to reduce the voltage on node 43to one P channel threshold voltage is very small and the time requiredto reduce the voltage on node 43 to one P channel threshold voltage isvery small. Thus transistors 17 and 22 do not provide any reaction ofconsequence to transistor 13 becoming conductive in response to signal*F switching to a logic high.

Transistor 13 being conductive in response to signal *F being a logichigh is significant in the operation of circuit 51. Transistor 13 beingconductive is then an initial condition for the case in which signal INswitches to a logic high. Thus when signal IN switches to a logic high,the consequent rise in voltage of node 43 is immediately coupled to thebases of transistors 17 and 22 so that signal *F switches to a logic lowwith minimal delay. Additionally, the current paths are terminated aftersignal *F has switched to the logic low so that there are no d.c. pathsbetween Vcc and ground after the logic states of signals F and *F havebeen established. Especially for rapid cycle times between changes insignals IN and *IN, node 43 remains very near the logic high voltageeven when signal IN is a logic low. Thus node 43 need only be raisedslightly in voltage in response to signal IN switching to a logic high.This also is advantageous for speed. Node 43 can only drop in voltageone Vbe below the ECL logic low. Transistor 11 becomes conductive toprevent any drop below one Vbe below the logic low of signal IN.

Reference voltage VR is chosen to ensure that transistor 12 is notconductive for the case when transistor 11 can be conductive with alogic low input but is conductive for the case in which signal IN is alogic high. Transistor 11 is not conductive until node 43 drops to oneVbe below the base of transistor 11. Thus, for the case in which signalIN is a logic low, transistor 13 can be prevented from becomingconductive simultaneously with transistor 11 becoming conductive byselecting reference voltage VR to be greater than one P channelthreshold voltage below one Vbe below the ECL logic low. The voltage onnode 43 is then not sufficiently greater than the voltage at the gate oftransistor 12 for transistor 12 to become conductive when signal IN isan ECL logic low. On the other hand transistor 12 must be conductive forthe case in which signal IN is an ECL logic high. Node 43 is one Vbebelow the ECL logic high when signal IN is a logic high. Consequently,reference voltage VR must be less than one P channel threshold voltagebelow one Vbe below the ECL logic high. Because there is about a onevolt difference between an ECL logic high and an ECL logic low,reference voltage VR is chosen to be a few tenths of a volt below one Pchannel threshold voltage below one Vbe below the ECL logic highvoltage. The ECL logic high voltage, a Vbe, and a P channel thresholdvoltage are all references readily available in the particularintegrated circuit so that reference generator 15 providing reference VRwithin the desired constraints is easily attainable using bandgapreference techniques.

Thus, it will be apparent to those skilled in the art that the disclosedinvention may be modified in numerous ways and may assume manyembodiments other than those specifically set out and described above.For example, the voltage on the gate of transistor could be clockedinstead of being a constant reference voltage so long as transistor 12was non-conductive when signal IN was a logic low and was conductivewhen signal IN was a logic high. An advantage of clocking the gate oftransistor 12 would be that transistor 12 could be more conductive whensignal IN was a logic high. A disadvantage is increased circuitcomplexity. Another example of a possible variation is to use PNPtransistors in place of P channel transistors 12 and 24. Accordingly, itis intended by the appended claims to cover all modifications of theinvention which fall within the true spirit and scope of the invention.

We claim:
 1. An ECL to CMOS translator for receiving first and secondcomplementary ECL input signals and providing a first output signal atCMOS levels, comprising:first control means for coupling the first ECLinput signal to a first node if said first ECL input signal is in afirst logic state and for preventing said first ECL input signal frombeing coupled to the first node if said first ECL input signal is in asecond logic state; first coupling means, coupled to a second node andthe first control means, for coupling the first node to a third node inresponse to the second node being at the first logic state; a firsttransistor having a control electrode coupled to the third node, a firstcurrent electrode coupled to a first power supply terminal, and a secondcurrent electrode coupled to the second node, said first transistor forproviding said first output signal on said second node at the secondlogic state in response to the third node receiving said first ECL inputsignal at said first logic state; second control means for coupling thesecond ECL input signal to a fourth node if said second ECL input signalis in a first logic state and for preventing said second ECL inputsignal from being coupled to the fourth node if said second ECL inputsignal is in a second logic state; second coupling means, coupled to afifth node and the second control means, for coupling the fourth node toa sixth node in response to the fifth node being at the first logicstate; a second transistor having a control electrode coupled to thesixth node, a first current electrode coupled to the first power supplyterminal, and a second current electrode coupled to the fifth node; anda third transistor having a control electrode coupled to the fifth node,a first current electrode coupled to a second power supply terminal, anda second current electrode coupled to the second node, said thirdtransistor providing said output signal at the second logic state onsaid second node in response to receiving the first logic state on saidfifth node.
 2. The translator of claim 1 further comprising:a fourthtransistor having a control electrode coupled to the second node, afirst current electrode coupled to the second power supply terminal, anda second current electrode coupled to the fifth node.
 3. The translatorof claim 2, wherein the first and second transistors are NPNtransistors.
 4. The translator of claim 3, wherein the third and fourthtransistors are P channel transistors.
 5. In an integrated circuithaving an ECL circuit for providing a first ECL output signal at a logiclow at a voltage at least 2 volts above a voltage at a first powersupply terminal and a logic high at a voltage greater than the voltageof the logic low, a translator circuit for providing a voltage at ornear the potential at the first power supply terminal on an output nodein response to the ECL output signal switching to the logic high,comprising:a first NPN transistor having a base for receiving the firstECL output signal, a collector coupled to a second power supply terminalfor receiving a voltage greater than the voltage present at the secondpower supply terminal, and an emitter; first control means for couplingthe emitter of the first NPN transistor to an intermediate node inresponse to said first ECL output signal switching to the logic high andfor preventing said emitter of the first NPN transistor from beingcoupled to the intermediate node when said first ECL output signal is atthe logic low; and a second transistor having a control electrodecoupled to the intermediate node, a first current electrode coupled tothe first power supply terminal, and a second current electrode coupledto the output node, whereby the output node is coupled to the firstpower supply terminal in response to the first ECL output signalswitching to the logic high.
 6. The translator circuit of claim 5further comprising decoupling means, interposed between the intermediatenode and the control electrode of the first NPN transistor, fordecoupling the intermediate node from the control electrode of thesecond transistor in response to the output node switching to thevoltage at or near the voltage at the first power supply terminal. 7.The translator circuit of claim 5 wherein the control means is a Pchannel transistor having a first current electrode coupled to theemitter of the first NPN transistor, a control electrode for receiving areference voltage, and a second current electrode coupled to theintermediate node.
 8. The translator circuit of claim 7 wherein thefirst NPN transistor is characterized as having Vbe and the P channeltransistor is characterized as having a P channel threshold voltage, andthe control means further comprises reference generator means forgenerating the reference voltage at a voltage greater than one Vbe belowthe P channel threshold voltage below the voltage of the logic low ofthe first ECL output signal and less than one Vbe below the P channelthreshold voltage below the voltage of the logic high of the first ECLoutput signal.
 9. The translator circuit of claim 5 further comprisinglogic high means for receiving a second ECL output signal complementaryto the first ECL output signal and coupling the second power supplyterminal to the output node in response to said second ECL output signalswitching to the logic high.
 10. In an integrated circuit having an ECLswitching for providing a first ECL output signal at a logic low atleast 2 volts above a potential at a first power supply terminal and alogic high at a voltage greater than the voltage of the logic low, atranslator circuit for providing a voltage at or near the potential atthe first power supply terminal on an output node in response to the ECLoutput signal switching to the logic high, comprising:a first NPNtransistor having a base for receiving the first ECL output signal, acollector coupled to a second power supply terminal for receiving avoltage greater than the voltage present at the second power supplyterminal, and an emitter; a first P channel transistor having a firstcurrent electrode coupled to the emitter of the first NPN transistor, acontrol electrode for receiving a reference voltage, and a secondcurrent electrode; a second P channel transistor having a first currentelectrode coupled to the second current electrode of the first P channeltransistor, a control electrode, and a second current electrode; a firstresistor having a first terminal coupled to the second current electrodeof the second P channel transistor, and a second terminal; a second NPNtransistor having a base coupled to the second terminal of the firstresistor, an emitter coupled to the first power supply terminal, and acollector coupled to the output node; an inverter having an inputcoupled tothe output node, and an output coupled to the controlelectrode of the second P channel transistor.
 11. The translator circuitof claim 10 wherein the first NPN transistor is characterized as havingVbe and the second P channel transistor is characterized as having a Pchannel threshold voltage, and the control means further comprisesreference generator means for generating the reference voltage at avoltage greater than one Vbe below the P channel threshold voltage belowthe voltage of the logic low of the first ECL output signal and lessthan one Vbe below the P channel threshold voltage below the voltage ofthe logic high of the first ECL output signal.
 12. The transistorcircuit of claim 10 further comprising a second resistor having a firstterminal coupled to the base of the second NPN transistor, a secondterminal coupled to the first power supply terminal.
 13. The transistorcircuit of claim 12 further comprising a third NPN transistor having abase coupled to the the first terminal of the first resistor, acollector coupled to the emitter of the first NPN transistor, and anemitter coupled to the base of the second NPN transistor.
 14. Thetranslator circuit of claim 13 further comprising a first N channeltransistor having a control electrode coupled to the output of theinverter, a first current electrode coupled to the output of theinverter, and a second current electrode coupled to the first powersupply terminal.
 15. The translator circuit of claim 14 furthercomprising a diode having an anode coupled to the first terminal of thefirst resistor, and a cathode coupled to the collector of the second NPNtransistor.
 16. The translator circuit of claim 10 for further providinga voltage at or near the second power supply terminal on the output nodein response to a complementary ECL signal, further comprising:a thirdNPN transistor having a base for receiving the complementary ECL signal,a collector coupled to a second power supply terminal, and an emitter; athird P channel transistor having a first current electrode coupled tothe emitter of the third NPN transistor, a control electrode forreceiving the reference voltage, and a second current electrode; afourth P channel transistor having a first current electrode coupled tothe second current electrode of the third P channel transistor, acontrol electrode, and a second current electrode; a second resistorhaving a first terminal coupled to the second current electrode of thefourth P channel transistor, and a second terminal; a fourth NPNtransistor having a base coupled to the second terminal of the secondresistor, an emitter coupled to the first power supply terminal, and acollector coupled to a control node; a second inverter having an inputcoupled to the control node, and an output coupled to the controlelectrode of the fourth P channel transistor; and a fifth P channeltransistor having a first current electrode coupled to the second powersupply terminal, a control electrode coupled to the control node, and asecond current electrode coupled to the output node.
 17. The translatorcircuit of claim 16 further comprising a sixth P channel transistorhaving a first current electrode coupled to the second power supplyterminal, a control electrode coupled to the output node, and a secondcurrent electrode coupled to the control node.
 18. The translatorcircuit of claim 17 wherein the first NPN transistor is characterized ashaving a Vbe and the first P channel transistor is characterized ashaving a P channel threshold voltage, and the control means furthercomprises reference generator means for generating the reference voltageat a voltage greater than one Vbe below the P channel threshold voltagebelow the voltage of the logic low of the first ECL output signal andless than one Vbe below the P channel threshold voltage below thevoltage of the logic high of the first ECL output signal.